module top_bsh_32(
    input               clk,
    input               rst_n,
    input   [31:0]      data_in,
    input               dir,
    input   [4:0]       sh,
    output  reg[31:0]   data_out
);
    wire  [31:0]    data_out_r;
    reg   [31:0]    data_in_r;
    reg             dir_r;
    reg   [4:0]     sh_r;

bsh_32 ubsh_32(
    .data_out   (data_out_r),
    .data_in    (data_in_r),
    .dir        (dir_r),
    .sh         (sh_r)
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        data_out      <=    32'b0;
        data_in_r     <=    32'b0;
        dir_r         <=    1'b0;
        sh_r          <=    5'b0;
    end
    else begin
        data_out      <=    data_out_r;
        data_in_r     <=    data_in;
        dir_r         <=    dir;
        sh_r          <=    sh;
    end
end    

endmodule